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0.8% accurate quad uv/ov positive/negative voltage supervisor adm12914 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2010 analog devices, inc. all rights reserved. features quad undervoltage/overvoltage (uv/ov) positive/negative supervisor supervises up to two negative rails adjustable uv and ov input thresholds industry leading threshold accuracy over the extended temperature range: 0.8% 1 v buffered reference output open-drain uv and ov reset outputs adjustable reset timeout with disable option outputs guaranteed down to v cc of 0.9 v glitch immunity 62 a supply current 16-lead qsop package specified from ?40c to +125c applications server supply monitoring fpga/dsp core and i/o voltage monitoring telecommunications equipment medical equipment functional block diagram timer timer v cc logic output logic ref 500mv 500mv 500mv 500mv mux sel gnd adm12914 vh1 uv ov ref latch/dis vl1 vh2 vl2 vh3 vl3 vh4 vl4 08265-001 figure 1. general description the adm12914 is a quad voltage supervisory ic ideally suited for monitoring multiple rails in a wide range of applications. each monitored rail has two dedicated input pins, vhx and vlx, which allows each rail to be monitored for both undervoltage (uv) and overvoltage (ov) conditions with high threshold accuracy of 0.8%. common active low undervoltage ( uv ) and overvoltage ( ov ) pins are shared by each of the monitored voltage rails. the adm12914 includes a 1 v buffered reference output, ref, that acts as an offset when monitoring a negative voltage. the three-state sel pin determines the polarity of the third and fourth inputs, that is, it configures the device to monitor positive or negative supplies. the device incorporates an internal shunt regulator that enables the device to be used in higher voltage systems. this feature requires a resistor to be placed between the main supply rail and the v cc pin to limit the current flow into the v cc pin at a level no greater than 10 ma. the adm12914 uses the internal shunt regulator to regulate v cc if the supply line exceeds the absolute maximum ratings. the adm12914 is available in two models. the adm12914-1 offers a latching overvoltage output that can be cleared by toggling the latch input pin. the adm12914-2 has a disable pin that can override and disable both the uv and the ov output signals. the adm12914 is available in a 16-lead qsop package. the device is specified over the extended temperature range of ?40c to +125c.
adm12914 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configurations and function descriptions ........................... 5 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 voltage supervision ...................................................................... 9 polarity configuration ................................................................. 9 monitoring pin connections .................................................... 10 threshold accuracy ................................................................... 10 voltage monitoring example .................................................... 11 power-up and power-down ..................................................... 12 uv / ov timing characteristics ............................................... 12 timer capacitor selection ........................................................ 12 uv and ov rise and fall times .............................................. 13 uv / ov output characteristics ........................................... 13 glitch immunity ......................................................................... 13 undervoltage lockout (uvlo) ............................................... 13 shunt regulator .......................................................................... 13 ov latch (adm12914-1) ......................................................... 13 disable (adm12914-2) ............................................................. 14 typical applications ....................................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 6/10rev. b to rev. c changed v cc of 1 v to v cc of 0.9 v in features section ............. 1 2/10rev. a to rev. b changes to figure 17 and figure 18 ............................................. 10 12/09rev. 0 to rev. a changes to shunt regulator section ............................................ 13 9/09revision 0: initial version
adm12914 rev. c | page 3 of 16 specifications t a = ?40c to +125c. typical values at t a = 25c, unless otherwise noted. v cc = 3.3 v, vlx = 0.45 v, vhx = 0.55 v, latch = v cc , sel = v cc , dis = open, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions/comments shunt regulator v cc shunt regulator voltage v shunt 6.3 6.6 6.8 v i cc = 5 ma v cc shunt regulator load regulation v shunt 150 mv i cc = 2 ma to 10 ma supply supply voltage 1 v cc 2.3 v shunt v minimum v cc output valid v ccr(min) 0.9 v dis = 0 v supply undervoltage lockout v cc(uvlo) 1.94 2 2.06 v dis = 0 v, v cc rising supply undervoltage lockout hysteresis v cc(hyst) 15 25 35 mv dis = 0 v supply current i cc 62 100 a v cc = 2.3 v to 6.0 v reference output reference output voltage v ref 0.994 1 1.008 v i vref = 1 ma undervoltage/overvoltage characteristics undervoltage/overvoltage threshold v uot 496 500 504 mv v cc = 2.3 v to 6.0 v undervoltage/overvoltage threshold to output delay t uod 100 200 350 s vhx = v uot ? 5 mv or vlx = v uot + 5 mv vhx, vlx input current i vhl 10 na uv / ov timeout period t uoto 7.5 8.5 10.5 ms c timer = 1 nf ov latch clear input ov latch clear threshold input high v latch (ih) 1.2 v ov latch clear threshold input low v latch (il) 0.8 v latch input current i latch 50 na v latch > 0.5 v disable input dis input high v dis(ih) 1.2 v dis input low v dis(il) 0.8 v dis input current i dis 1.25 2 2.75 a v dis > 0.5 v timer characteristics timer pull-up current i timer(up) ?1.7 ?2.1 ?2.5 a v timer = 0 v timer pull-down current i timer(down) 1.7 2.1 2.5 a v timer = 1.6 v timer disable voltage v timer(dis) ?180 ?270 mv referenced to v cc output voltage output voltage high uv / ov v oh 1 v v cc = 2.3 v; i uv / ov = ?1 a output voltage low uv / ov v ol 0.1 0.3 v v cc = 2.3 v; i uv / ov = 2.5 ma 0.01 0.15 v v cc = 0.9 v; i uv = 100 a three-state input sel low level input voltage v il 0.4 v high level input voltage v ih 1.4 v pin voltage when left in high-z state v z 0.8 0.9 1.0 v i sel = 10 a sel high, low input current i sel 25 a maximum sel input current i sel(max) 30 a sel tied to v cc or gnd 1 the maximum voltage on the v cc pin is limited by the input current. the v cc pin has an internal 6.5 v shunt regulat or and, therefore, a low impedance supply exceeding 6 v may exceed the maximum allowable input current. when operating from a higher supply than 6 v, always use a droppe r resistor.
adm12914 rev. c | page 4 of 16 absolute maximum ratings table 2. parameter rating v cc ?0.3 v to +6 v uv , ov ?0.3 v to +16 v timer ?0.3 v to (v cc + 0.3 v) vlx, vhx, latch , dis, sel ?0.3 v to +7.5 v i cc 10 ma reference load current (i ref ) 1 ma i uv , i ov 10 ma storage temperature range ?65c to +150c operating temperature range ?40c to +125c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. thermal resistance package type ja unit 16-lead qsop 104 c/w esd caution
adm12914 rev. c | page 5 of 16 pin configurations and function descriptions vh1 1 vl1 2 vh2 3 vl2 4 v cc 16 timer 15 sel 14 latch 13 vh3 5 vl3 6 vh4 7 uv 12 ov 11 ref 10 vl4 8 gnd 9 adm12914-1 top view (not to scale) 08265-002 figure 2. adm12914-1 pin configuration v cc 16 vh1 1 vl1 2 timer 15 vh2 3 sel 14 vl2 4 dis 13 vh3 5 uv 12 vl3 6 ov 11 vh4 7 ref 10 gnd 9 adm12914-2 top view (not to scale) 08 265-011 vl4 8 figure 3. adm12914-2 pin configuration table 4. pin function descriptions pin no. adm12914-1 adm12914-2 mnemonic description 1, 3 1, 3 vh1, vh2 voltage high input 1 and voltage high input 2. if the voltage monitored by vh1 or vh2 drops below 0.5 v, an undervoltage condition is detected. connect to v cc when not in use. 2, 4 2, 4 vl1, vl2 voltage low input 1. if the voltage monitored by vl1 or vl2 rises above 0.5 v, an overvoltage condition is detected. tie to gnd when not in use. 5, 7 5, 7 vh3, vh4 voltage high input 3 and voltage high input 4. the polarity of these inputs is determined by the state of the sel pin (see table 5 ). when the monitored input is configured as a positive voltage and the voltage monitored by vh3 and vh4 drops below 0.5 v, an under- voltage condition is detected. conversely, when the input is configured as a negative voltage and the input drops below 0.5 v, an overvoltage condition is detected. connect to v cc when not in use. 6, 8 6, 8 vl3, vl4 voltage low input 3 and voltage low input 4. th e polarity of these inputs is determined by the state of the sel pin (see table 5 ). when the monitored input is configured as a positive voltage and the voltage monitored by vl3 or vl4 rises above 0.5 v, an overvoltage condition is detected. conversely, when the in put is configured as a negative voltage and the input rises above 0.5 v, an undervoltage condition is detected. tie to gnd when not in use. 9 9 gnd device ground. 10 10 ref buffered reference output. this pin is a 1 v reference that is used as an offset when monitoring negative voltages. this pin can source or sink 1 ma, and drive loads up to 1 nf. larger capacitive loads may lead to instability. leave unconnected when not in use. 11 11 ov overvoltage reset output. ov is asserted low if a negative polarity input voltage drops below its associated threshold or if a positive polarity input voltage exceeds its threshold. the adm12914-1 allows ov to be latched low. the adm12914-2 holds ov low for an adjustable timeout period determined by the timer capacitor. this pin has a weak pull-up to v cc and can be pulled up to 16 v externally. le ave this pin unconnected when not in use 12 12 uv undervoltage reset output. uv is asserted low if a negative polarity input voltage exceeds its associated threshold or if a positive polarity input voltage drops below its threshold. uv is held low for an adjustable timeout period se t by the external capacitor tied to the timer pin. the uv pin has a weak pull-up to v cc and can be pulled up to 16 v externally via an external pull-up resistor. leave this pin unconnected when not in use. 13 n/a 1 latch ov latch bypass input/clear pin. when pulled high, the ov latch is cleared. when held high, the ov output has the same delay and output characteristics as the uv output. when pulled low, the ov output is latched when asserted. (applies only to the adm12914-1.) n/a 1 13 dis ov and uv disable input. when pulled high, the ov and uv outputs are held high irrespective of the state of the vhx and vlx in put pins. however, if a uvlo condition occurs, the ov and uv outputs are asserted. this pin has a weak internal pull-down (2 a) to gnd. leave this pin unconnected when not in use. (applies only to the adm12914-2.) 14 14 sel input polarity select. this three-state input pin allows the polarity of vh3, vl3, vh4, and vl4 to be configured. connect this pin to v cc or gnd, or leave it open to select one of three possible input polarity configurations (see table 5 ).
adm12914 rev. c | page 6 of 16 pin no. adm12914-1 adm12914-2 mnemonic description 15 15 timer adjustable reset delay timer. connect an external capacitor to the timer pin to program the reset timeout delay. refer to figure 15 in the typical performance characteristics section. connect this pin to v cc to bypass the timer. 16 16 v cc supply voltage. v cc operates as a direct supply for voltages up to 6 v. for voltages greater than 6 v, it operates as a shunt regulator. a dropper resistor must be used in this configuration to limit the current to less than 10 ma. when used without the resistor, the voltage at this pin must not exceed 6 v. a 0.1 f bypass capacitor or greater should be used. 1 n/a means not applicable.
adm12914 rev. c | page 7 of 16 typical performance characteristics 0.505 0.503 0.504 0.501 0.502 0.499 0.500 0.497 0.498 0.495 0.496 ?40 ?25 ?10 125110958065 50 3520 5 temperature (c) threshold voltage, v uot (v) 0 8265-012 figure 4. input threshold voltage vs. temperature 90 50 temperature (c) i cc (a) 85 80 75 70 65 60 55 ?40 ?25 ?10 125110958065503520 5 v cc = 6v v cc = 3.3v v cc = 2.3v 08265-013 figure 5. supply current vs. temperature 6.80 6.40 temperature (c) v cc (v) 6.75 6.70 6.65 6.60 6.55 6.50 6.45 200a 1ma 2ma 5ma 10ma ?40 ?25 ?10 125 11095 80 65503520 5 08265-014 figure 6. v cc shunt voltage vs. temperature 6.80 6.40 024681 i cc (ma) v cc (v) 0 6.75 6.70 6.65 6.60 6.55 6.50 6.45 +25c ?40c +85c 08265-015 figure 7. v cc shunt voltage vs. i cc 1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 temperature (c) reference voltage, v ref (v) ?40 ?25 ?10 125110 95 8065503520 5 08265-016 figure 8. buffered referenc e voltage vs. temperature 1000 900 800 700 600 500 400 300 200 100 0 0.1 1 10 100 comparator overdrive (% of v uot ) transient duration (s) v cc = 2.3v v cc = 6v reset asserted above the line 08265-017 figure 9. transient duration vs. comparator overdrive
adm12914 rev. c | page 8 of 16 14 13 12 11 10 9 8 7 temperature (c) uv/ov timeout period, t uoto (ms) ?40 ?25 ?10 12511095 80 65503520 5 0 8265-018 figure 10. uv / ov timeout period vs. temperature 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 supply voltage, v cc (v) uv voltage (v) with 10k ? pull-up without pull-up 08265-019 figure 11. uv output voltage vs. v cc 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 01234 supply voltage, v cc (v) 5 uv voltage (v) vhx = 0.55v sel = v cc 08265-020 figure 12. uv output voltage vs. v cc 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 0123456 supply voltage, v cc (v) pull-down current i uv (ma) vhx = 0.45v sel = v cc uv = 150mv uv = 50mv 08265-021 figure 13. i sink , i uv vs. v cc 1000 900 800 700 600 500 400 300 200 100 0 051 0 i sink (ma) 1 5 +85c +25c ? 40c uv/ov, v ol (mv) 0 8265-022 figure 14. uv / ov voltage output low vs. output sink current 10k 1k 100 10 1 0.1 1 10 100 1000 timer pin capacitance c timer (nf) uv/ov timeout period, t uoto (ms) 08265-023 figure 15. uv / ov timeout period vs. capacitance
adm12914 rev. c | page 9 of 16 theory of operation voltage supervision the adm12914 supervises up to four voltage rails for under- voltage and overvoltage conditions. two pins, vhx and vlx, are assigned to monitor each rail, one for overvoltage detection and the other for undervoltage detection. each pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 0.5 v voltage reference with very high threshold accuracy of 0.8%. the device is specified over the extended operating temperature range from ?40c to +125c. the output of each of the internal undervoltage comparators is tied to a common uv output pin. likewise, the outputs of the internal overvoltage comparators are tied to a common ov output pin. vh1 1.8v vl1 vh2 vl2 vh3 vl3 vh4 vl4 sel timer uv ov latch/dis ref gnd v cc adm12914 2.5v 3.3v 5 v system psu 08265-003 figure 16. typical applications diagram polarity configuration the adm12914 is capable of monitoring supply voltages of both positive and negative polarities. the sel pin is a three- state pin that determines the polarity of input 3 and input 4. as summarized in table 5 , the sel pin is connected to either gnd or v cc , or is not connected. when an input is configured to monitor a positive voltage, using the three resistor scheme that is shown in figure 17 , vhx is connected to the high-side tap of the resistor divider and vlx is connected to the low-side tap of the resistor divider. conversely, when an input is configured to monitor a negative voltage, uvx and ovx are swapped internally. the negative voltage for monitoring is then connected as shown in figure 18 . vhx remains connected to the high-side tap and vlx remains connected to the low-side tap. within this configuration, an undervoltage condition occurs when the monitored voltage is less negative than the programmed threshold, and an overvoltage condition occurs when the monitored voltage is more negative than the programmed threshold. table 5. polarity configuration input 3 input 4 sel pin polarity uv condition ov condition polarity uv condition ov condition connected to v cc positive vh3 < 0.5 v vl3 > 0.5 v positive vh4 < 0.5 v vl4 > 0.5 v left unconnected positive vh3 < 0.5 v vl3 > 0.5 v negative vl4 > 0.5 v vh4 < 0.5 v connected to gnd negative vl3 > 0.5 v vh3 < 0.5 v negative vl4 > 0.5 v vh4 < 0.5 v
adm12914 rev. c | page 10 of 16 monitoring pin connections positive voltage monitoring scheme when monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by v m , i m is the nominal current through the resistor divider, v ov is the over- voltage trip point, and v uv is the undervoltage trip point. 0.5v uvx vhx v m vlx ovx adm12914 r x v ph v pl r z r y 0 8265-004 figure 17. positive undervoltage/overvoltage monitoring configuration figure 17 illustrates the positive voltage monitoring input con- nection. three external resistors, r x , r y , and r z , divide the positive voltage for monitoring,v m , into high-side voltage, v ph , and low-side voltage, v pl . the high-side voltage is con- nected to the corresponding vhx pin and the low-side voltage is connected to the corresponding vlx pin. to trigger an overvoltage condition, the low-side voltage (in this case, v pl ) must exceed the 0.5 v threshold on the vlx pin. the low-side voltage, v pl , is given by the following equation: v5.0 = ? ? ? ? ? ? ? ? ++ = z yx z ov pl rrr r vv also, m m z yx i v rrr =++ therefore, r z , which sets the desired trip point for the overvoltage monitor, is calculated using the following equation: () () () m ov m z iv v r )5.0( = (1) to trigger the undervoltage condition, the high-side voltage, v ph , must exceed the 0.5 v threshold on the vhx pin. the high-side voltage, v ph , is given by the following equation: v5.0 = ? ? ? ? ? ? ? ? ++ + = z yx z y uv ph rrr rr vv because r z is already known, r y can be expressed as follows: () () () z m uv m y r iv v r ? = )5.0( (2) when r y and r z are known, r x is calculated using the following formula: ( ) () y z m m x rr i v r ??= (3) if v m , i m , v ov , or v uv change, each step must be recalculated. negative voltage monitoring scheme figure 18 shows the circuit configuration for negative supply voltage monitoring. to monitor a negative voltage, a 1 v reference voltage is required to connect to the end node of the voltage divider circuit. this reference voltage is generated internally and is output through the ref pin. 0.5v ovx vhx v m vlx uvx ref adm12914 r z v nh v nl r x r y 0 8265-005 figure 18. negative undervoltage/overvoltage monitoring configuration the equations described previously in the positive voltage monitoring scheme section need some minor modifications for use with negative voltage monitoring. the 1 v reference voltage is added to the overall voltage drop; it must therefore be sub- tracted from v m , v uv , and v ov before using each in the previous equations. to monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between the 1 v reference voltage and the negative supply voltage into high-side voltage, v nh , and low-side voltage, v nl . similar to the positive voltage monitoring scheme, the high-side voltage, v nh , is connected to the corresponding vhx pin and the low-side voltage, v nl , is connected to the corresponding vlx pin. refer to the volt age monitoring example section for further information. threshold accuracy the reset threshold accuracy is fundamental, especially at lower voltage levels. consider an fpga application that requires a 1 v core voltage input with a tolerance of 5%, where the supply has a specified regulation, for example, 2.6%. as shown in figure 19 , to ensure the supply is within the fpga input voltage requirement range, its voltage level must be monitored for uv and ov condi- tions. the voltage swing on the supply itself causes the voltage band available for setting the monitoring threshold to be quite narrow. in this example, the threshold voltages, including the
adm12914 rev. c | page 11 of 16 tolerances, must fit within a monitor region of just 0.024 v. the adm12914 device with 0.1% resistors can achieve this level of accuracy. 1.05v +5% tolerance ?5% tolerance 1.026v 1v core voltage 0.974v 0.95v uv v oltage time 2.4% range for ov monitoring 2.4% range for uv monitoring +2.6% supply regulation ?2.6% supply regulation t uoto 08265-006 figure 19. monitoring accuracy example voltage monitoring example to illustrate how the adm12914 device works in a real-world application, consider the 1 v input example shown in figure 19 , with the addition of a ?5 v rail. the first step is to choose the current flow through both voltage divider circuits, for example, 5 a. for the 1 v 5% input, due to the specified 2.6% regulation of the supply, the uv and ov threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respec- tively; in this case, on the 3.8% points of the supply, which are 0.962 v for the uv threshold and 1.038 v for ov threshold. input these values into equation 1 to equation 3 as follows: k 5.96 )105)(038.1( )1)(5.0( 6 = ? (1) insert the value of r z into equation 2. k7.41 k 5.96 )105)(962.0( )1)(5.0( 6 ? = ? (2) then substitute the calculated values for r z and r y into equation 3. k 5.96k7.41 k 5.96 105 1 6 ?? = ? (3) this design approach meets the application specifications. as described previously, the 1 v rail is specified with an input requirement of 5% and a supply tolerance of 2.6%. this effectively means the ov threshold of the monitoring device, including all the tolerance factors, must fit within the 1.026 v to 1.05 v range. similarly, the uv threshold range must be between 0.95 v and 0.974 v. the four worst-case scenarios of minimum and maximum undervoltage and overvoltage thresholds are calculated as follows: minimum overvoltage threshold ? ? ? ? ? ? ? ? + ?+? +?= %)1.0( %)1.0(%)1.0( 1%)8.05.0( _ z y x minov r r r v v ? ? ? ? ? ? ? ? + += )001.1)(500,96( )999.0)(7410500,96( 1496. 0 =1.029 v > 1.026 v maximum overvoltage threshold ? ? ? ? ? ? ? ? ? +++ ++= %)1.0( %)1.0(%)1.0( 1%)8.05.0( _ z y x maxov r r r v v = 1.047 v < 1.05 v the maximum and minimum overvoltage threshold values reside within the 1.026 v to 1.05 v range specified. the minimum and maximum undervoltage thresholds are calculated as follows: minimum undervoltage threshold ? ? ? ? ? ? ? ? +++ ? +?= %)1.0(%)1.0( %)1.0( 1%)8.0v5.0( _ z y x minuv r r r v = 0.9557 v > 0.95 v maximum undervoltage threshold ? ? ? ? ? ? ? ? ?+? + ++= %)1.0(%)1.0( %)1.0( 1%)8.0v5.0( _ z y x maxuv r r r v = 0.9729 v < 0.974 v these values fit within the specified undervoltage monitoring range. all four worst-case scenarios satisfy the tolerance requirement; therefore, the design approach is valid. adm12914 vh1 v cc 5v 1v rail gnd vl1 vl3 vh3 ref uv sel ov ? 5v rai l 1.09m ? 14.3k ? 93.1k ? 96.5k ? 7.41k ? 96.5k ? 08265-007 figure 20. positive and negative supply monitor example
adm12914 rev. c | page 12 of 16 next, consider a ?5 v input, which is specified with a 12% input. the threshold accuracy required by the supply is chosen to be within 5% of the ?5 v rail. the uv and ov threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respectively. in this case, on the 8.5% points of the supply, which is ?4.575 v for the uv threshold and ?5.425 v for the ov threshold. the negative voltage scheme configuration requires that the 1 v reference voltage be accounted for in equation 1 to equation 3. the 1 v reference voltage is subtracted from v m , v uv , and v ov , and the absolute value of the result is taken. equation 1 becomes ( ) () () k 1.93 6 1051425.5 15)5.0( ? ?? ?? = z r insert the value of r z into equation 2 ( ) () () k 3.14 k 1.93 1051575.4 15)5.0( 6 ? ?? ?? = ? y r to c a l c u l ate r x , insert the value of r z and r y into equation 3. () ()() m 09.1k1.93k3.14 105 15 6 ?? ?? = ? x r power-up and power-down on power-up, when v cc reaches 1 v, the active low uv output asserts and the ov output pulls up to v cc . when the voltage on the v cc pin reaches 1 v, the adm12914 is guaranteed to assert uv low and ov high. when v cc exceeds 1.9 v (minimum), the vhx and vlx inputs take control. when v cc and each of the vhx inputs are valid, an internal timer begins. subsequent to an adjustable time delay, uv weakly pulls high. uv /ov timing characteristics uv is an active low output. it asserts when any of the four moni- tored voltages is below its associated threshold. when the voltage on the v cc pin is greater than 2 v, an internal timer holds uv low for an adjustable period, t uoto , after the voltages on all the monitoring rails rise above their thresholds. this allows time for all monitored power supplies to stabilize after power-up. similarly, any monitored voltage that falls below its threshold initiates a timer reset, and the internal timer restarts once all the monitoring rails rise above their thresholds. the uv and ov outputs are held asserted after all faults have cleared for an adjustable timeout period, determined by the value of the external capacitor attached to the timer pin. timer capacitor selection the uv and ov timeout period on the adm12914 is program- mable via the external timer capacitor, c timer , placed between the timer pin and ground. the timeout period, t uoto , is calculated using the following equation: c timer = ( t uoto )(115)(10 ?9 ) f/sec refer to figure 15 in the typical performance characteristics section, which illustrates the delay time as a function of the timer capacitor value. a minimum capacitor value of 10 pf is required. the chosen timer capacitor must have a leakage current that is less than the 1.7 a timer pin charging current. to bypass the timeout period, connect the timer pin to v cc . v hx monitor timing t uod t uoto vhx uv v uot 1v vhx monitor timing (timer pin tied to v cc ) t uod t uod vhx uv v uot 1v notes 1. when an input is configured to monitor a negative voltage, vhx triggers an overvoltage condition. 08265-026 figure 21. vhx positive voltage monitoring timing diagrams v lx monitor timing t uod t uoto vlx ov v uot 1v vlx monitor timing (timer pin tied to v cc ) t uod t uod vlx ov v uot 1v notes 1. when an input is configured to monitor a negative voltage, vlx triggers an undervoltage condition. 08265-027 figure 22. vlx positive voltage monitoring timing diagrams
adm12914 rev. c | page 13 of 16 uv and ov rise and fall times the uv or ov output rise times (from 10% to 90%) can be approximated using the following equation: t r 2.2( r pull-up )( c load ) where: r pull-up is the internal weak pull-up resistance with an approx- imate value of 400 k at room temperature with v cc > 1 v. c load is the external load capacitance on the output pin. when a fault occurs, the uv or ov output fall time can be expressed as t f 2.2( r pull-down )( c load ) where r pull-down is the internal pull-down resistance, which is approximately 50 . assuming a load capacitance of 150 pf, the fall time is 16.5 ns. uv / ov output characteristics both the ov and uv outputs have strong pull-down to ground and weak internal pull-up to v cc . this permits the pins to behave as open-drain outputs. when the rise time on the pin is not critical, the weak pull-up removes the requirement for an external pull-up resistor. the open-drain configuration allows for wire-oring of outputs, which is particularly useful when more than one signal needs to pull down on the output. at v cc = 1 v, a maximum v ol = 0.15 v at uv is guaranteed. at v cc = 1 v, the weak pull-up current on ov is almost turned on. consequently, if the state and pull-up strength of the ov pin is important at very low v cc , an external pull-up resistor of no more than 100 k is advised. by adding an external pull-up resistor, the pull-up strength on the ov pin is greater. therefore, if it is connected in a wire-ored configuration, the pull-down strength of any single device must account for this additional pull-up strength. glitch immunity the adm12914 is immune to shor t transients that may occur on the monitored voltage rails. the device contains internal filtering circuitry that provides immunity to fast transient glitches. figure 9 illustrates glitch immunity performance by showing the maximum transient duration without causing a reset pulse. glitch immunity makes the adm12914 suitable for use in noisy environments. undervoltage lockout (uvlo) the adm12914 has an undervoltage lockout circuit that monitors the voltage on the v cc pin. when the voltage on v cc drops below 1.94 v (minimum), the circuit activates. the uv output is asserted and the ov output is cleared and is not allowed to assert. when v cc recovers, uv exhibits the same timing characteristics as though an undervoltage condition had occurred on the inputs. shunt regulator the adm12914 is powered via the v cc pin. the v cc pin can be directly connected to a voltage rail of up to 6 v. in this mode, the supply current of the device does not exceed 100 a. an internal shunt regulator allows the adm12914 to operate at voltage levels greater than 6v by simply placing a dropper resistor in series between the supply rail and the v cc pin to limit the input current to less than 10 ma. once the supply voltage, v in , has been established, an appropriate value for the dropper resistor can be calculated. begin by determining the maximum supply current required, i cctotal , by adding the current drawn from the reference and/or the pull resistors between the outputs and the v cc pin to the maximum specified supply current. the minimum and maximum shunt regulator voltage specified in table 1, v shunt min and v shunt max , are also required in the following calculations. calculate the maximum and minimum dropper resistor values cctotal shuntmax inmin max i v v r ? = 100 shuntmin inmax min vv r ? = based on these values, choose a real-world resistor value within this range. then, given the specified accuracy of this resistor, calculate the minimum and maximum real resistor value variation, r realmin and r realmax , respectively. the maximum device power is calculated as follows: () + ? ? ? ? ? ? ? ? = total real shuntmax in shuntmax devicemax icc r vv v p min max cctotal shuntmax iv to check that the calculated value of the resistor will be acceptable, calculate the maximum device temperature rise devicemax ja risemax p temp = add this value to the ambient operating temperature. if the resistor value is acceptable, the result will lie within the specified operating temperature range of the device. ov latch (adm12914-1) if an overvoltage condition occurs when the latch pin is pulled low, the ov pin latches low. pulling latch high clears the latch. if an ov condition clears while latch is high, the latch is bypassed and the ov pin behaves in the same way as the uv pin, with an identical timeout period. if the latch pin is pulled low while the timeout period is active, the ov pin latches low, as in normal operation.
adm12914 rev. c | page 14 of 16 disable (adm12914-2) pulling the dis pin high disables both the uv and ov outputs, and forces both outputs to remain weakly pulled high, regard- less of any faults that are detected at the inputs. if a uvlo condition is detected, the uv output is asserted and pulls low; however, the timeout function is bypassed. as soon as the uvlo condition clears, the uv output pulls high. to guarantee normal operation when the pin is left unconnected, dis has a weak 2 a internal pull-down current.
adm12914 rev. c | page 15 of 16 typical applications vh1 1.8v vl1 vh2 vl2 vh3 vl3 vh4 vl4 sel timer uv ov latch/dis ref gnd v cc adm12914 2.5v 3.3v 5 v system psu 45.3k ? 3.05k ? 120k ? 27.1k ? 1.82k ? 111k ? 34.8k ? 2.34k ? 200k ? 33.6k ? 2.37k ? 312k ? 08265-008 figure 23. typical application diagram for monitoring 5 v, 3.3 v, 2.5 v, and 1.8 v with 1.5% supply tolerance and 5% input tole rance requirement vh1 ?12v vl1 vh2 vl2 vh3 vl3 vh4 vl4 sel timer uv ov latch/dis ref gnd v cc adm12914 +12v system psu 12k? 1420k ? 51.7k ? 1k? 83.5k ? 5.62k ? 1.98m ? 0 8265-009 figure 24. typical application diagram for monitoring 12 v with 1.5% supply tolerance and 5% input tolerance requirement; ?12 v with 3% supply tolerance and 15% input tolerance requirement
adm12914 rev. c | page 16 of 16 outline dimensions compliant to jedec standards mo-137-ab 012808-a controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) figure 25. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option adm12914-1arqz ?40c to +125c 16-lead shri nk small outline package [qsop] rq-16 adm12914-1arqz-rl7 ?40c to +125c 16-lead sh rink small outline package [qsop] rq-16 adm12914-2arqz ?40c to +125c 16-lead shri nk small outline package [qsop] rq-16 ADM12914-2ARQZ-RL7 ?40c to +125c 16-lead sh rink small outline package [qsop] rq-16 1 z = rohs compliant part. ?2009-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08265-0-6/10(c)

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